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Integrated Circuit Systems, Inc.
ICS951402 Advance Information
Programmable Timing Control HubTM for P4TM processor
Recommended Application: ATI chipset, P4 system, Banias system Output Features: * 2 - Pairs of differential CPUCLKs (differential current mode) * 1 - SDRAM @ 3.3V * 8 - PCI @3.3V (selectable 33/66 MHz) (2 free-running) * 2 - AGP @ 3.3V * 2- 48MHz, @3.3V fixed. * 1- 24/48MHz, @3.3V selectable by I2C (Default is 24MHz) * 3- REF @3.3V, 14.318MHz. Features/Benefits: * Support for Intel Banias power management features * Programmable output frequency, divider ratios, output rise/ falltime, output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * Supports spread spectrum for EMI reduction; default is spread spectrum ON.
Pin Configuration
VDDREF FS0/REF0 FS1/REF1 FS2/REF2 GNDREF X1 X2 GND VDD *VttPWR_GD/PD# PCI66/33#_SEL PCI_STOP#* VDDPCI FS3/PCICLK_F0 FS4/PCICLK_F1 PCICLK0 PCICLK1 GNDPCI VDDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK5 GNDPCI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDSDR SDRAM_OUT GNDSDR CPU_STOP#* CPUCLKT1 CPUCLKC1 VDDCPU GNDCPU CPUCLKT0 CPUCLKC0 IREF GND AVDD SCLK SDATA GNDAGP AGPCLK0 AGPCLK1 VDDAGP AVDD48 48MHz_0 48MHz_1 24_48MHz/SEL24_48#MHz** GND48
48-Pin TSSOP & SSOP
* These inputs have a 120K pull up to VDD. ** These inputs have a 120K pull down to GND.
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz (0:1) 24_48MHz
Skew Requirements
PCI-PCI AGP-AGP CPU-AGP CPU-PCI
3
ICS951402
<350ps <350ps <500ps <500ps <1ns <1ns
REF (2:0)
CPU DIVDER
Stop
2 2
CPUCLKT (1:0) CPUCLKC (1:0)
AGP-PCI AGP leading CPU-SDRAM
SDATA SCLK FS (4:0) PD# PCI_STOP# CPU_STOP# PD#/Vtt_PWRGD PCI66/33#SEL 24_48SEL#
SDRAM
Control Logic
PCI DIVDER Stop
1
SDRAM_OUT
Power Groups
6
PCICLK (5:0) PCICLK_F (1:0)
Config. Reg.
2
AGP DIVDER
2
AGP (1:0) I REF
VDDCPU = CPU VDDPCI = PCICLK_F, PCICLK VDDSD = SDRAM AVDD48 = 48MHz, 24MHz, fixed PLL AVDD = Analog Core PLL VDDAGP= AGP VDDREF = Xtal, REF
0660--05/05/05 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
Pin Description
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 PIN NAME VDDREF FS0/REF0 FS1/REF1 FS2/REF2 GNDREF X1 X2 GND VDD *VttPWR_GD/PD# TYPE PWR I/O I/O I/O PWR IN OUT PWR PWR IN DESCRIPTION Ref, XTAL power supply, nominal 3.3V Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Ground pin for the REF outputs. Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Power supply, nominal 3.3V This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the device into a low power state. Selects all PCI clock frequencies to be 33Mhz or 66Mhz. 0 = 33Mhz , 1 = 66Mhz Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low Power supply for PCI clocks, nominal 3.3V Frequency select latch input pin / 3.3V PCI free running clock output. Frequency select latch input pin / 3.3V PCI free running clock output. PCI clock output. PCI clock output. Ground pin for the PCI outputs Power supply for PCI clocks, nominal 3.3V PCI clock output. PCI clock output. PCI clock output. PCI clock output. Ground pin for the PCI outputs Ground pin for the 48MHz outputs 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz. 48MHz clock output. 48MHz clock output. Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V Power supply for AGP clocks, nominal 3.3V AGP clock output AGP clock output Ground pin for the AGP outputs Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. 3.3V Analog Power pin for Core PLL Ground pin. This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Complementary clock of differential pair CPU outputs. This clock is 180 degrees out of phase with the SDRAM clock. True clock of differential pair CPU outputs. This clock is in phase with the SDRAM clock Ground pin for the CPU outputs Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. This clock is 180 degrees out of phase with the SDRAM clock. True clock of differential pair CPU outputs. This clock is in phase with the SDRAM clock Stops all CPUCLK besides the free running clocks Ground pin for the SDRAM outputs. SDRAM seed clock output for external buffer Supply for SDRAM clocks, nominal 3.3V.
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
PCI66/33#_SEL PCI_STOP#* VDDPCI FS3/PCICLK_F0 FS4/PCICLK_F1 PCICLK0 PCICLK1 GNDPCI VDDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK5 GNDPCI GND48 24_48MHz/SEL24_48#MHz** 48MHz_1 48MHz_0 AVDD48 VDDAGP AGPCLK1 AGPCLK0 GNDAGP SDATA SCLK AVDD GND IREF
IN IN PWR I/O I/O OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR I/O OUT OUT PWR PWR OUT OUT PWR I/O IN PWR PWR OUT
39 40 41 42 43 44 45 46 47 48
0660--05/05/05
CPUCLKC0 CPUCLKT0 GNDCPU VDDCPU CPUCLKC1 CPUCLKT1 CPU_STOP#* GNDSDR SDRAM_OUT VDDSDR
OUT OUT PWR PWR OUT OUT IN PWR OUT PWR
2
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
Table 1: Clock Power Management Truth Table
Byte 6 Bit 6 Byte 6 Bit 7 PD# CPU_ STOP Stoppable CPU (Not free-run) Non-stop CPU (Free-run) Note
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
IREF x 2 IREF x 2 IREF x 6 RUN Hi Z Hi Z Hi Z RUN Hi Z Hi Z IREFx6 RUN Hi Z Hi Z HI Z RUN
IREF x 2 IREF x 2 RUN RUN IREF x 2 IREF x 2 RUN RUN Hi Z Hi Z RUN RUN Hi Z Hi Z RUN RUN
Non Tri-state Mode CPU_stop# Tri-state Mode PD# & Tri-state Mode PD# & CPU_stop# Tri-state Mode
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3
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
General I2C serial interface information for the ICS951402 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit Slave Address D2(H) WR WRite T Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
*See notes on the following page.
0660--05/05/05
4
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
Serial Configuration Command Bitmap
CPU MHz FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 100.00 133.34 200.01 166.65 100.00 133.34 133.16 166.45 105.00 140.00 66.67 175.00 109.99 146.65 210.00 183.27 99.51 132.68 199.02 165.85 99.51 132.68 132.59 165.73 99.39 132.51 198.77 165.64 99.39 132.51 132.36 165.45 SDRAM MHz 100.00 133.34 200.01 166.65 133.34 100.00 166.45 133.16 105.00 140.00 66.67 175.00 109.99 146.65 210.00 183.27 99.51 132.68 199.02 165.85 132.68 99.51 165.73 132.59 99.39 132.51 198.77 165.64 132.51 99.39 165.45 132.36 3V66 MHz PCI MHz REF MHz USB/DOT MHz 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 With Spread Enabled...
66.67 66.67 66.67 66.66 66.67 66.67 66.58 66.58 70.00 70.00 66.67 70.00 73.33 73.33 70.00 73.31 66.34 66.34 66.34 66.34 66.34 66.34 66.29 66.29 66.26 66.26 66.26 66.25 66.26 66.26 66.18 66.18
33.33 33.33 33.33 33.33 33.33 33.33 33.29 33.29 35.00 35.00 33.33 35.00 36.66 36.66 35.00 36.65 33.17 33.17 33.17 33.17 33.17 33.17 33.15 33.15 33.13 33.13 33.13 33.13 33.13 33.13 33.09 33.09
14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
SpreaD OFF OR Center spread +/-0.3%
Down Spread -0.6%
Down Spread -0.8%
0660--05/05/05
5
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
I2C Table: Reserved Register
Byte 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Control Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
1 1 1 1 1 1 1 1
I2C Table: Reserved Register
Byte 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Control Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
1 1 1 1 1 1 1 1
I2C Table: Reserved Register
Byte 2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Control Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
1 1 1 1 1 1 1 1
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6
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
I2C Table: Reserved Register
Byte 3
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
Pin #
-
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Control Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
1 1 1 1 1 1 1 1
I C Table: Functionality and Frequency Select Register
Byte 4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Pin #
-
Name FS3 FS2 FS1 FS0 FS Source
Bit 2 FS4 SS_EN Bit 1 All Outputs Bit 0 Note: If Byte4 bit1 = 0 then FS4=0
2
Control Function Freq Select Bit 7 Freq Select Bit 6 Freq Select Bit 5 Freq Select Bit 4 Frequency H/W or IIC Select Freq Select Bit 2 SPREAD Enable Output Control
Type RW RW RW RW RW RW RW RW
0
1
PWD 0 0 0 0 0 0 1 0
See Frequency Table Latch Input IIC
See Frequency Table OFF ON Normal Tri-state
I C Table: Output Control and Read Back Register
Byte 5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # 31 32 26 -
Name AGP1 AGP0 24_48#SEL FS4RB FS3RB FS2RB FS1RB FS0RB
Control Function Output Control Output Control 24 or 48 Select FS4 Read back FS3 Read back FS2 Read back FS1 Read back FS0 Read back
Type RW RW RW R R R R R
0 Disable Disable 48MHz -
1 Enable Enable 24MHz -
PWD 1 1 X X X X X X
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7
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
I2C Table: Output Control Register
Byte 6
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
40,39 44,43
Name
CPU_STOP# PD# PCI_F0 PCI_F1 CPUT/C_0 CPUT/C_1 CPUT/C_0 CPUT/C_1
Control Function
CPU Stop Status PD# Status Free-run Control Free-run Control Free-run Control Free-run Control Output Control Output Control
Type
RW RW RW RW RW RW RW RW
0
1
PWD
1 1 0 0 1 1 1 1
See Table 1: Truth Table on page 3 Free Free Free Free Disable Disable Not free Not free Not free Not free Enable Enable
I C Table: Output Control Register
2
Byte 7
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # 15 14 23 22 21 20 17 16
Name PCICLK_F1 PCICLK_F0 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
I2C Table: Byte Count Register
Byte 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
Control Function
Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes.
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
0 0 0 0 1 1 1 1
0660--05/05/05
8
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
I C Table: Watchdog Timer Register
2
Byte 9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
Pin #
-
Name
WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
Control Function Type
These bits represent X*293ms the watchdog timer will wait before it goes to alarm mode. Default is 16 X 293ms =4.688 seconds RW RW RW RW RW RW RW RW
0
-
1
-
PWD
0 0 0 1 0 0 0 0
I C Table: WD Timer Control Register
Byte 10
Bit 7 Bit 6 Bit 5
Pin #
-
Name
M/NEN WDEN WDStatus
Control Function
M/N Programming
Enable Watchdog Enable WD Status Control
Type
RW RW RW RW RW RW RW RW
0
Latched Inputs Disable OFF -
1
IIC Prog. B (11:17)
PWD
0 0 0 1 0 0 0 0
Enable
ON
WD SF4 Bit 4 WD SF3 Bit 3 WD SF2 Bit 2 WD SF1 Bit 1 WD SF0 Bit 0 Note: If Byte4 bit1 = 0 then FS4=0
Writing to these bit will
configure the safe frequency as Byte 0 Bit (6:0)
-
I2C Table: VCO Frequency Control Register
Byte 11
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
N Div8 M Div6 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0
Control Function
N Divider Bit 8 The decimal representation of M Div (6:0) is equal to reference divider value. Default at power up = latch-in or Byte 0 Rom table.
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
X X X X X X X X
0660--05/05/05
9
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
I2C Table: VCO Frequency Control Register
Byte 12
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0
Control Function
The decimal representation of N Div (8:0) is equal to VCO divider value. Default at power up = latch-in or Byte 0 Rom table.
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
X X X X X X X X
I2C Table: Spread Spectrum Control Register
Byte 13
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Control Function
These Spread Spectrum bits will program the spread percentage. It is recommended to use ICS Spread % table for spread programming.
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
X X X X X X X X
I2C Table: Spread Spectrum Control Register
Byte 14
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
Reserved Reserved Reserved SSP12 SSP11 SSP10 SSP9 SSP8
Control Function
Reserved Reserved Reserved It is recommended to use ICS Spread % table for spread programming.
Type
R R R RW RW RW RW RW
0
-
1
-
PWD
X X X X X X X X
0660--05/05/05
10
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
I2C Table: Output Divider Control Register
Byte 15
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
SD Div3 SD Div2 SD Div1 SD Div0 CPU Div3 CPU Div2 CPU Div1 CPU Div0
Control Function
SDRAM divider ratio can be configured via these 4 bits individually. CPU divider ratio can be configured via these 4 bits individually.
Type
RW RW RW RW RW RW RW RW
0
1
PWD
See Table 2: Divider Ratio Combination Table See Table 2: Divider Ratio Combination Table
X X X X X X X X
Table 2: CPU, SDRAM, AGP and PCI66 Divider Ratio Combination Table
Divider (3:2)
Bit 00 0000 0001 0010 0011 Address 1 2 3 5 7 Div 01 0100 0101 0110 0111 Address 2 4 6 10 14 Div 10 1000 1001 1010 1011 Address 4 8 12 20 28 Div 11 1100 1101 1110 1111 Address MSB 8 16 24 40 56 Div
Divider (1:0)
00 01 10 11 LSB
Table 3: PCI33 Divider Ratio Combination Table
Divider (3:2)
Bit 00 0000 0001 0010 0011 Address 1 4 3 5 7 Div 01 0100 0101 0110 0111 Address 2 8 6 10 14 Div 10 1000 1001 1010 1011 Address 4 16 12 20 28 Div 11 1100 1101 1110 1111 Address MSB 8 32 24 40 56 Div
Divider (1:0)
0660--05/05/05
00 01 10 11 LSB
11
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
I2C Table: Output Divider Control Register
Byte 16
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
AGP Div3 AGP Div2 AGP Div1 AGP Div0 Reserved Reserved Reserved Reserved
Control Function
AGP divider ratio can be configured via these 4 bits individually Reserved Reserved Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
1
PWD
See Table 2: Divider Ratio Combination Table -
X X X X X X X X
I C Table: Output Divider Control Register
2
Byte 17
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
Pin #
-
Name
AGPINV Reserved SDINV CPUINV PCIDiv3 PCIDiv3 PCIDiv3 PCIDiv3
Control Function
AGP Phase Invert
Type
RW RW RW RW RW RW RW RW
0
Default Default Default
1
Inverse Inverse Inverse
PWD
Reserved
SDRAM Phase Invert CPU Phase Invert
X X X X X X X X
PCI divider ratio can be configured via these 4 bits individually
See Table 2 & 3: Divider Ratio Combination Table
I C Table: Group Skew Control Register
Byte 18
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
CPUSkw3 CPUSkw2 SDSkw3 SDSkw2 Reserved Reserved Reserved Reserved
Control Function
CPUT Skew Control SDRAM Skew Control Reserved Reserved Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
1
PWD
See 2-bit Skew Control at table 4 See 2-bit Skew Control at table 4 -
1 0 0 1 1 1 1 1
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Integrated Circuit Systems, Inc.
ICS951402 Advance Information
Table 4:Skew Specification on Output Mode
Bit3 Bit2 Bit1 Bit0 Skew in ps
0 0 1 1
0 1 0 1
X X X X
X X X X
500 750 1000 1250
I2C Table: Group Skew Control Register
Byte 19
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
Reserved Reserved Reserved Reserved AGPSkw3 AGPSkw2 Reserved Reserved
Control Function
Reserved Reserved Reserved Reserved AGP Skew Control Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
1
PWD
0 0 0 0 0 0 0 0
See 2-bit Skew Control at table 4 -
I2C Table: Group Skew Control Register
Byte 20
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
PCISkw3 PCISkw2 Reserved Reserved PCISkw1 PCISkw0 Reserved Reserved
Control Function
PCI_F [1:0] Skew Control Reserved Reserved PCI [5:0] Skew Control Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
1
PWD
See 2-bit Skew Control at table 4 See 2-bit Skew Control at table 4 -
0 0 0 0 0 0 0 0
0660--05/05/05
13
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
I2C Table: Slew Rate Control Register
Byte 21
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
24_48Slw1 24_48Slw0 AGPSlw1 AGPSlw0 Reserved Reserved REFSlw1 REFSlw0
Control Function
24_48 Slew Rate Control AGP Slew Rate Control Reserved Reserved REF Slew Rate Control
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
0 0 0 0 0 0 0 0
I C Table: Slew Rate Control Register
2
Byte 22
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
SDSlw1 SDSlw0 Reserved Reserved PCISlw1 PCISlw0 PCISlw1 PCISlw0
Control Function
SDRAM Slew Rate Control Reserved Reserved PCI_F Slew Rate Control PCI Slew Rate Control
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
0 0 0 0 0 0 0 0
I C Table: Output Control Register
2
Byte 23
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0660--05/05/05
Pin #
27 47 28 26 4 3 2
Name
Reserved 48MHz_1 SDRAM 48MHz_0 24_48MHz REF2 REF1 REF0
Control Function
Reserved Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type
RW RW RW RW RW RW RW
0
Disable Disable Disable Disable Disable Disable Disable
1
Enable Enable Enable Enable Enable Enable Enable
PWD
X 1 1 1 1 1 1 1
14
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
I2C Table: Reserved Control Register
Byte 24
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Control Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
0 0 0 0 0 0 0 0
I2C Table: Reserved Control Register
Byte 25
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Control Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
-
1
-
PWD
0 0 0 0 0 0 0 0
0660--05/05/05
15
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Input High Voltage Input Low Voltage Input High Current VIH VIL IIH IIL1 Input Low Current IIL2 Operating Supply Current I DD3.3OP I DD3.3OP Powerdown Current Input Frequency Pin Inductance Input Capacitance1 Clk Stabilization1,2 I DD3.3PD Fi Lpin CIN COUT CINX TSTAB tPZH,tPZL Delay
1 2 1
CONDITIONS
MIN 2 VSS 0.3 -5 -5 -200 229 220
TYP
MAX VDD +0.3 0.8 5
UNITS V V mA mA
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = Full load; Select @ 100 MHz CL =Full load; Select @ 133 MHz IREF=5 mA VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From PowerUp or deassertion of PowerDown to 1st clock. Output enable delay (all outputs) Output disable delay (all outputs)
230 233 38.1 14.32
360 360 45 7 5 6 45 1.8 10 10
mA mA mA MHz nH pF pF pF ms ns ns
27
36 1
1 1
tPHZ,tPLZ
Guaranteed by design, not 100% tested in production. See timing diagrams for buffered and un-buffered timing requirements.
0660--05/05/05
16
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
Electrical Characteristics - CPU (0.7V Select)
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Current Source Output VO = Vx Zo1 Impedance I OH = -1 mA Output High Voltage VOH3 Output Low Voltage V OL3 I OL = 1 mA Voltage High VHigh Statistical measurement on Voltage Low VLow single ended signal using Max Voltage Measurement on single ended Vovs signal using absolute value. Min Voltage Vuds Crossing Voltage (abs) Vcross(abs) Variation of crossing over all Crossing Voltage (var) d-Vcross edges V OL = 0.175V, VOH = 0.525V Rise Time tr Fall Time tf VOH = 0.525V VOL = 0.175V Rise Time Variation d-t r Fall Time Variation d-t f Measurement from differential Duty Cycle dt3 wavefrom VT = 50% Skew t sk3 Jitter, Cycle to cycle
1 2
MIN 3000 2.4 660 -150 -450 250
TYP
MAX
UNITS V
710 0
0.4 850 150 1150 550 140
mV mV mV mV ps ps ps ps % ps ps
175 175
240 242
700 700 125 125 55 100 150
45
51 50 76
t jcyc-cyc
1
VT = 50%
Guaranteed by design, not 100% tested in production. I OWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - AGP
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance VO = VDD*(0.5) RDSP11 1 I OH = -1 mA Output High Voltage VOH Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
MIN 12 2.4
TYP 66.66 33
MAX 55 0.55
UNITS MHz W V V mA mA ns ns % ps ps
V OL1 I OH1 I OL1 t r11 t f11 dt11 t sk11 t jcyc-cyc
1
I OL = 1 mA = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V
OH@MIN
V
-33 30 0.5 0.5 45 1.38 1.45 54.4 243 139
-33 38 2 2 55 250 250
VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 3V66
Guaranteed by design, not 100% tested in production.
0660--05/05/05
17
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance VO = VDD*(0.5) RDSP11 1 Output High Voltage I OH = -1 mA VOH Output Low Voltage Output High Current Output Low Current 48DOT Rise Time 48DOT Fall Time VCH 48 USB Rise Time VCH 48 USB Fall Time 48 DOT Duty Cycle VCH 48 USB Duty Cycle 48 DOT Jitter USB to DOT Skew VCH Jitter
1
MIN 20 2.4
TYP 48 48
MAX 60 0.4
UNITS MHz W V V mA mA ns ns ns ns % % ps ns ps
V OL1 I OH1 I OL1 t r11 t f11 t r11 t f11 dt11 dt11 t jcyc-cyc t sk11 t jcyc-cyc
1 1
I OL = 1 mA = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V
OH@MIN
V
-29 29 0.5 0.5 1 1 45 45 0.6 0.8 1.2 1.3 52.8 53.5 183 0.43 223
-23 27 1 1 2 2 55 55 350 1 350
VOH = 2.4 V, V OL = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V (0 OR 180 degrees) VT = 1.5 V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD =VDDL 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter1
1
SYMBOL RDSP2A RDSN2A VOH2A VOL2A IOH2A IOL2A t r2A1 t f2A1 dt2A1 t cyc-cyc
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) I OH = -28 mA I OL = 19 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN TYP MAX UNITS 10 10 2.4 20 20 0.4 -42 33 0.5 0.5 45 2.0 2 55 250.0 V V mA mA ns ns % ps
Guaranteed by design, not 100% tested in production.
0660--05/05/05
18
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance VO = VDD*(0.5) RDSP11 1 Output High Voltage I OH = -1 mA VOH Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
MIN 20 2.4
TYP 48
MAX 60 0.4
UNITS MHz W V V mA mA ns ns % ps
V OL1 I OH1 I OL1 t r11 t f11 dt11 t jcyc-cyc
1
I OL = 1 mA = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V
OH@MIN
V
-29 29 1 1 45 1.25 1.15 53
-23 27 2 2 55 1000
VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V
Guaranteed by design, not 100% tested in production.
0660--05/05/05
19
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
0660--05/05/05
20
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP# PCI_F 33MHz PCI 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms
CPU_STOP# CPUT CPUC
0660--05/05/05
21
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0 8 0 8 aaa -0.10 -.004 VARIATIONS
-Ce
b SEATING PLANE
N 48
10-0039
D mm. MIN 12.40 MAX 12.60 MIN .488
D (inch) MAX .496
Reference Doc.: JEDEC Publication 95, MO-153
aaa C
Ordering Information
ICS951402yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0660--05/05/05
22
Integrated Circuit Systems, Inc.
ICS951402 Advance Information
N
c
300 mil SSOP SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1 b c D E E1 e h L N a VARIATIONS N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
A A1
D mm. MIN 15.75 MAX 16.00 MIN .620
D (inch) MAX .630
48
-C-
e
Reference Doc.: JEDEC Publication 95, MO-118
b SEATING PLANE .10 (.004) C
10-0034
Ordering Information
ICS951402yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0660--05/05/05
23

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